AEi Systems specializes in PDN assessments for the linear and switching regulators driving your FPGAs and ASICs. Without A PDN assessment it is possible that IC load steps will cause your regulators to exceed their regulation limits. Not accounting for the PDN impedance between regulators and fast digital IC loads can be disastrous and result in intermittent operation that can be data dependent, hard to test for, and difficult to fix. Show below are papers on the left and videos on the right that we have published on this topic.

April 26, 2018: Paper - Lessons Learned about Power Integrity
Power Integrity is driving design performance. On the other hand, most designers and programs have not realized they need to have a Power Integrity plan. With each new generation of high speed digital and RF chips and circuitry, designs are expected to perform at higher frequencies while the supply voltages are being reduced to meet new power efficiency goals. As the result, circuits have become increasingly sensitive to power supply noise and power delivery network (‘PDN’) impedance mismatches. As voltage margins have decreased, even minor variations in the supply voltage interacting with the VMRs and PCB designs have large detrimental impacts on system performance. This also means that heritage results are no longer necessarily valid as a performance baseline. Therefore, the ability to test, characterize, model, simulate and optimize the performance of your power supply, PDN, and their integral components, is crucial for a successful design. In this paper you will learn via some examples, why these are critical concerns and how they can be avoided.

SSO Noise Effects in RTAX FPGAs - PDF w/Notes
SSO Noise is major concern for Power Integrity. It is necessary to understand and predict SSO performance. However, test data/models are inadequate and lead to over-design and poor design choices. Thorough characterization and modeling are necessary in order to properly assess and predict performance. Accurate modeling of the VDD droop, ground bounce and PDN is now possible. Worst case prediction of SSO noise is now possible. This presentation discusses how.

SSO Noise Effects in A54SX32A FPGAs
The design of a Power Distribution Network (PDN) to support FPGAs with large numbers of fast, Simultaneously Switching Outputs (SSO) is currently an area with little definitive test data, and therefore little definitive analysis or correlated models. AEi Systems has developed a methodology for measuring the worst-case effects of SSO on the PDN of FPGAs and carried out laboratory testing using the commonly used part, the Microsemi A54SX32A.

As presented at MAPLD 2014

Reducing Noise in Power Distribution Networks on Time and In Budget
Power Integrity, distribution, and management are essential for system functionality and performance. This presentation addresses power regulation in terms of power distribution network design with respect to best noise practices in the system using the tools of noise modeling and analysis on boards, packages, and silicon. It emphasizes the modeling and analysis of supply noise and its sources as well as its impact on overall system performance.

The target impedance concept has been used by the industry for a number of years. It is the basis of a simple and robust design process, but it assumes a smooth flat impedance profile. Looking out from the silicon, the impedance profile is never flat, which results in higher noise. Excitation patterns that can create near worst-case time-domain responses of a power distribution network has gained a lot of interest in recent years. The peak value of the step response, the response to a repetitive excitation at a resonance peak, as well as the absolute worst-case time-domain response are potentially producing results much worse than target impedance alone would imply. This presentation discusses how these are related, how the target impedance concept can be applied under such circumstances, as well as providing tips for recognizing and avoiding rogue waves. Rogue wave measurements will also be shown.

Two common PDN measurement questions
Why do you calibrate the 2-port measurement with a 1Ω shunt resistor, and, why do you need DC blockers on both ports?

Increase range in 2-port impedance measurements
Measuring the output impedance of wideband op amps presents a formidable challenge because of their high DC gain, which results in low closed-loop output impedance at low frequencies. Above the frequency of the op amp's internal dominant pole, however, its output impedance becomes inductive. Fortunately, you can overcome this problem with some simple techniques.

Improve Performance And Reduce Cost
By carefully matching the VRM, PCB planes, and load circuits to each other and to the required impedance magnitude, a flat PDN impedance can be created while minimizing circuit board area. The optimization also minimizes the use of expensive low-ESR capacitors and low-impedance voltage regulators.

PCB characteristics affect PDN performance
The basic design rules for PDN teach us that the best performance is obtained from a uniform, flat impedance profile. This is one reason that power supply stability is important, since a power supply with poor stability results in impedance peaks, which degrade the flat impedance profile and the performance of the circuit being powered.

Measure PDN on a budget
As the use of microcontrollers, CPUs and FPGAs continues to grow, more engineers are facing challenges with their PDN design and measurement. Typically, PDN measurements are performed using a network analyzer. A 1-port measurement can be used for impedance levels above a few hundred mΩ.

PDN Basics –Paralleling Tantalum and Ceramic Capacitors Can Be Risky
Paralleling capacitors to achieve high frequency sideband decoupling must take into account the performance characteristics of individual capacitors.

8 of 10 Design issues I find are due to a single problem
The vast majority of design issues are directly or indirectly attributable to control loop stability.

Why is PDN measured using a VNA and not an oscilloscope?
If PDN (Power Distribution Network) analysis is an assessment of the input power supply voltage to a CPU then why is it measured using a VNA and not an oscilloscope?

Predictive energy balance control for PDN applications
Design for Power integrity is central to high-speed and low-noise electronic circuits. To achieve optimum performance you need to maintain the power path impedance magnitude below some specific level, often referred to as the target impedance, and keep it as flat as possible. One of the more interesting topologies, applicable to good PDN design is the patented predictive energy balance (PEB) controller, developed and owned by Cognipower.

Five things every Engineer should know about PDN
Steve Sandler describes the Top 5 most important things that every Engineer should know about PDN

PDN Issues Occur in the Simplest of Circuits
This study focuses on a much smaller scale, addressing a very simple circuit that experiences related PDN issues. While the issues shown here may seem obvious to some, this is an excellent example of a very common problem.

Target impedance based solutions for PDN may not provide realistic assessment
One of the more common design techniques for power distribution networks (PDN) is the determination of the peak impedance that will assure that the voltage excursions on the power rail will be maintained within allowable limits, generally referred to as the target impedance.

May 2021: Video - The Unfortunate State of Power Integrity in Space Systems (Part 2)
Learn about the current state of Power Integrity analysis and test in the Space industry from PI Guru Steve Sandler. This video discusses the progression in complexity of today’s power distribution systems and how rad-hard FPGAs are placing greater emphasis on the assessment, test, and optimization of power electronics due to various challenges.

Charts: April 27, 2017: Video - The Unfortunate State of Power Integrity in Space Systems (Part 1)
This video slideshow is from a presentation by Steve Sandler at the 2017 Space Power Workshop in Manhattan Beach, CA on April 27, 2017. The importance of power integrity cannot be underestimated.

Power Integrity (‘PI’) is a hot topic in the commercial electronics world. The power integrity ecosystem is comprised of best design practices, measurement, modeling, co-simulation using EM techniques, WCCA, and proper test & measurement training. So it’s not surprising that power integrity is a critical technology for Space applications. However, it is often surprising how little attention power integrity is given in Space applications. The space design community, and both power IC and high speed digital parts suppliers, have been slow to recognize the importance of this critical area of design technology, its implementation, and its assessment, often extracting a huge price on system performance, scheduling, board spins, and system reliability. This session serves as an introduction to Power Integrity and why it can no longer be ignored. Specific examples are used to illustrate the current state-of-the-art vs. the current state within satellite systems.

In modern electronic systems, the performance of FPGAs, CPUs, and other high-speed logic devices depends on the power distribution networks or PDNs that power these devices. Within these PDNs, power converters in the form of point-of-load regulators (POLs), voltage regulator modules (VRMs), dc-dc converters, and linear regulators play a crucial role. Yet, many engineers who develop these power converters may be unfamiliar with PDN concepts and how power converters affect PDN and system performance. In this three-part video series, Steve Sandler introduces three basic PDN concepts that developers of board-level power solutions need to understand.

How to Design for Power Integrity: Measuring, Modeling, Simulating Capacitors and Inductors
The third video in the Picotest/Keysight How-To Design for Power Integrity series is now available. Power supply switching ripple and control loop phase margin are dominated by the output inductor and the bulk capacitors. Simple RLC capacitor and inductor models can result in a design with more capacitors than necessary adding to the design cost, consuming valuable circuit board real estate and degrading the control loop performance. Most capacitor datasheets provide very limited information, such as maximum ESR at 100kHz and not the desired information regarding typical values and frequency dependencies of the C, ESR, and ESL. This short video shows you how to make these measurements efficiently and how to use the results to create high fidelity models for simulation.

How to Design for Power Integrity: Selecting a VRM
Many signal and power integrity issues are the result of poor VRM selection. This critical selection is often made arbitrarily due to insufficient, incomplete or incorrect data. Costly design time and multiple board spins can be minimized by following a few simple guidelines and performing a few simple simulations and measurements early in the process. This video explains why one should avoid Voltage mode VRMs and shunt compensation for the VRM Error Amplifier. The better performance of a current mode VRM with series compensation for the Error Amplifier is clearly demonstrated with simulations and measurements.

How to Design for Power Integrity: Finding Power Delivery Noise Problems
In this extended video, Steve explains how rogue waves can ruin your power, how are the natural and forced responses different, how many cycles are required to achieve the maximum amplitude response, why target impedance is a valuable tool in PDN design, and how to recognize the PDN impedance characteristics that are predictors of the potential for a rogue wave.

Part 1: What Is PDN and Why It’s Important
In this 4-min. video, Steve explains what PDNs are and why they matter, particularly to developers of POLs and VRMs.

Part 2: Why It’s Important to Keep Impedance Flat
In this 6-min. segment, Steve discusses power converter output impedance and why designers of board-level power converters need to keep their output impedance curves flat.

Part 3: Impedance Matching Is Critical
In the last video, which runs 3 min., Steve explains why the output impedance of a power converter needs to be matched to the impedance of the PDN in which it is used.

Part 1: Why Stability Matters
In this How2Power video, Steve Sandler discusses the impact of power supply stability problems.

Part 2: Impedance Is the Critical Measurement
Whether your goal is to optimize system performance or to troubleshoot issues in distributed power systems, impedance measurement is an indispensable tool. In this 10 minute video, Steve Sandler discusses the value of impedance measurements and demonstrates their usefulness with two examples: one using vendor-supplied data for a voltage reference and another using ADS-generated data for a second-order control loop.

Part 3: Measuring Impedance Using Vector Network Analyzers, One-Port Tests
Vector network analyzers (VNAs) have always had measurement capabilities that looked like they would be particularly useful in assessing the performance of analog and power components and circuits. This video focuses on single-port measurements, describing how they can be applied to measure the impedance of low power circuits such as linear regulators, voltage references and op amps as well as semiconductors, capacitors, and inductors. Test set up requirements are discussed and example measurements are presented.

Part 4: Measuring Impedance Using Vector Network Analyzers, Two-Port Tests
This video explains making and interpreting two-port impedance measurements, particularly those in which the device under test is connected "in shunt through" with the VNA ports. This technique may also be used to measure the impedances of batteries, DC-DC converters, EMI filters, and other functions. Setup requirements such as 4-wire connections, a common-mode transformer, DC blockers, and AC versus DC coupling are explained in this video. Also discussed is the use of a preamp to measure impedances below 1 milliohm.

Part 5: Using Current Injectors
Previous videos in this series discussed the use of vector network analyzers (VNAs) to measure impedance using one- or two-port configurations. This video discusses another method of measuring impedance—the current injector method. Although not quite as accurate as the two-port VNA impedance measurement, the current injection technique has advantages including wide range (approx. 1 milliohm to thousands of ohms), the ability to measure in-system, and a suitability for measuring low-power devices such as op amps, voltage references, and voltage regulators.

Part 6: The Switch
System and power converter issues are frequently related to a converter's switching characteristics, which are most easily observed at the switching node. In this installment of the Troubleshooting Distributed Power Systems video series, Steve Sandler discusses the measurement and interpretation of switch node waveforms as observed in point-of-load regulators or POLs. He discusses the instrumentation requirements for measuring switch-node waveforms, why switch-node waveforms should be viewed using different time scales, and the impact of scope probes on measurements.

Part 7: Measuring Ripple
Circuit designers, particularly power supply designers, are frequently required to measure power supply ripple. Nevertheless, many engineers struggle with this measurement as sensitivity, selectivity, and bandwidth limitations degrade the accuracy of oscilloscope results.

Part 8: Making Time Domain Measurements
In previous videos, Sandler discussed measurement of power supply signals such a switch-node waveforms and output ripple. In this video, he delves further into time-domain measurements of power supply signals using oscilloscopes, sometimes in combination with specialized adapters such as current injectors.

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