SSO Noise is major concern for Power Integrity. It is necessary to understand and predict SSO performance. However, test data/models are inadequate and lead to over-design and poor design choices. Thorough characterization and modeling are necessary in order to properly assess and predict performance. Accurate modeling of the VDD droop, ground bounce, and PDN is now possible. Worst case prediction of SSO noise is now possible. This presentation discusses how.
You can download the presentation here - SSO Noise Effects in RTAX FPGAs
In modern electronic systems, the performance of FPGAs, CPUs, and other high-speed logic devices depends on the power distribution networks or PDNs that power these devices. Within these PDNs, power converters in the form of point-of-load regulators (POLs), voltage regulator modules (VRMs), dc-dc converters, and linear regulators play a crucial role. Yet, many engineers who develop these power converters may be unfamiliar with PDN concepts and how power converters affect PDN and system performance. In this three-part video series, Steve Sandler introduces three basic PDN concepts that developers of board-level power solutions need to understand.
Part 1: What Is PDN and Why It’s Important
In this 4-min. video, Steve Sandler explains what PDNs are and why they matter, particularly to developers of POLs and VRMs.
Part 2: Why It’s Important to Keep Impedance Flat
In this 6-min. segment, Steve discusses power converter output impedance and why designers of board-level power converters need to keep their output impedance curves flat.
Part 3: Impedance Matching Is Critical
In the last video, which runs 3 min., Steve explains why the output impedance of a power converter needs to be matched to the impedance of the PDN in which it is used.