ÿþ<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> <!-- ______ _____ _______ _______ _______ ______ __ __ _____ /\ | ____|_ _| / ____\ \ / / ____|__ __| ____| \/ |/ ____| / \ | |__ | | | (___ \ \_/ / (___ | | | |__ | \ / | (___ / /\ \ | __| | | \___ \ \ / \___ \ | | | __| | |\/| |\___ \ / ____ \| |____ _| |_ ____) | | | ____) | | | | |____| | | |____) | /_/ \_\______|_____| |_____/ |_| |_____/ |_| |______|_| |_|_____/ Author: SpinQ Studios - Imagination Designed Date: Nov 2010 Site: SpinQ.com --> <html xmlns="http://www.w3.org/1999/xhtml"> <head> <title>::AEi Systems - Analog HEAVY Lifting::</title> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" /> <link rel="Shortcut Icon" href="images/favicon.ico" /> <link rel="stylesheet" href="css/style.css" /> <script type="text/javascript" src="js/png.js"></script> <script type="text/javascript"> function imageRollover(img, imgSrc){ img.src = imgSrc; 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left: 15px; top: 0px; position: absolute;"> <p style="text-align: justify; width: 390px; left: 10px; top: 10px; position: absolute;"> <b style="font-size: large;">Board - Signal Integrity Analysis</b> <br /> <br /> <b>AEi Systems specializes in Board Analysis for all types of digital and mixed signal systems.</b> <br /> <br /> The "<b>BOARD CHECKOUT</b>" package is an EXHAUSTIVE validation of your board, layout, and interconnect performance. The "<b>BOARD CHECKOUT</b>" package includes the following analyses: </p> <div style="width: 400px; left: 15px; top: 140px; position: absolute;"> <p style="text-align: left; width: 380px; left: 20px; top: 0px; position: absolute;"> " Signal Integrity </p> <p style="text-align: left; width: 380px; left: 20px; top: 15px; position: absolute;"> " DC Interface Compatibility </p> <p style="text-align: left; width: 380px; left: 20px; top: 30px; position: absolute;"> " Decoupling/Fanout </p> <p style="text-align: left; width: 380px; left: 20px; top: 45px; position: absolute;"> " Critical Timing Relationships </p> <p style="text-align: left; width: 380px; left: 20px; top: 60px; position: absolute;"> " Crosstalk/Ground Plane Coupling </p> <p style="text-align: left; width: 380px; left: 20px; top: 75px; position: absolute;"> " Power Sequencing </p> </div> <p style="text-align: justify; width: 400px; left: 10px; top: 240px; position: absolute;"> <b>Signal Integrity Analysis</b> - Signal integrity (SI) analysis is an essential part of evaluating most of today s board designs. Increasingly, fast edge rates and design complexities in high speed (> 10MHz) PCBs impact performance in sometimes unseen ways. As ICs switch faster, designs suffer from signal degradation, including over/undershoot, ringing, glitching, crosstalk, and timing problems, which all must be accounted for along with the physical PCB implementation. A thorough and rigorous analysis is the only way to validate that a successful outcome is likely. </p> <p style="text-align: justify; width: 380px; left: 10px; top: 370px; position: absolute;"> <img src="signal/signal_01.jpg" width="326" height="224" alt="" /> </p> <p style="text-align: justify; width: 400px; left: 10px; top: 600px; position: absolute;"> Critical edge-detect (of potential edge-detect) signals must be identified and analyzed to guarantee that their transitions will be monotonic for the life of the mission. Overshoots and undershoots occurring while transitioning between states must be reduced to a safe level guaranteed by the specification or other reliability criteria. </p> <p style="text-align: justify; width: 380px; left: 10px; top: 680px; position: absolute;"> <b>Items Considered During a Signal Integrity Analysis</b> <br /> <br /> </p> <div style="width: 400px; left: 15px; top: 690px; position: absolute;"> <p style="text-align: left; width: 390px; left: 20px; top: 15px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 15px; position: absolute;"> Characteristic impedance of PWB </p> <p style="text-align: left; width: 390px; left: 20px; top: 30px; position: absolute;"> " </p> <p style="text-align: justify; width: 300px; left: 30px; top: 30px; position: absolute;"> IBIS model performance range exhibited by the Slow, Typical, and Fast versions </p> <p style="text-align: left; width: 390px; left: 20px; top: 55px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 55px; position: absolute;"> Propagation delays </p> <p style="text-align: left; width: 390px; left: 20px; top: 70px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 70px; position: absolute;"> PWB characteristic impedance and material </p> <p style="text-align: left; width: 390px; left: 20px; top: 85px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 85px; position: absolute;"> Package and die parasitics </p> <p style="text-align: left; width: 390px; left: 20px; top: 100px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 100px; position: absolute;"> Vias </p> <p style="text-align: left; width: 390px; left: 20px; top: 115px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 115px; position: absolute;"> Input capacitance to the ASIC and ICs </p> <p style="text-align: left; width: 390px; left: 20px; top: 130px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 130px; position: absolute;"> Pin contact inductance </p> <p style="text-align: left; width: 390px; left: 20px; top: 145px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 145px; position: absolute;"> Connecting wire between boards </p> </div> <p style="text-align: justify; width: 400px; left: 10px; top: 860px; position: absolute;"> <b>Interface Compatibility Analysis</b> - An interface analysis validates that each interface meets the output and input requirements to perform a given function. In digital circuits, a good example is to validate that TTL outputs are joined with TTL compatible inputs, and that the fanout requirements are met. </p> </div> </div> <div id="text-box-right_"> <div style="width: 375px; left: 15px; top: 415px; position: absolute;"> <p style="text-align: justify; width: 375px; left: 10px; top: 45px; position: absolute;"> <b>Decoupling/Fanout Analysis</b> - The objective of this analysis is to determine the adequacy of the external decoupling and estimate the switching noise levels inside of the ICs on the board. It also confirms that the local power supply decoupling noise is less than a designated amount for all drivers/receivers. Noise at the IC due to imperfect local decoupling and internal noise due to simultaneously switching outputs are also assessed. </p> <p style="text-align: justify; width: 375px; margin-left: 10px; margin-top: 160px;"> <b>Critical Timing Relationships</b> - The objective of this analysis is to examine the digital signals on the board in order to identify any potential timing issues. </p> <p style="text-align: justify; width: 375px; margin-left: 10px; margin-top: 10px;"> Propagation delays and both rising and falling edges are examined for timing deltas. </p> <p style="text-align: justify; width: 375px; margin-left: 10px; margin-top: 10px;"> <b>Cross-talk Analysis</b> computes the nominal and worst case crosstalk caused by interference between traces, between all possible combinations of aggressor/victim signals. The basic concept of crosstalk can be described as a fast transition on one or more signals, called  aggressors, which are coupled onto nearby signals ( victims ). Each signal is expected to be in a certain voltage range for proper operation. If the induced voltage exceeds a certain maximum value, sufficient to bring the signal level into the threshold range, a functional failure may occur. Some small levels of crosstalk are unavoidable in any practical digital design and must be simply accounted for in noise margin budgets for all signals. For a board analysis, the amount of noise generated by crosstalk on each net is used in the DC Compatibility analysis as a margin allocation specifically for the crosstalk. The analysis accounts for the exact geometry of all traces, pads, layer dimensions, etc. The IC I/O models used vary based on the part type, availability of appropriate models from the manufacturer, and other factors. </p> </div> <div style="width: 400px; height:430px; left: 15px; top: 10px; position: absolute; border:3px solid black;"> <p style="text-align: left; width: 400px; margin-left: 10px; margin-top: 10px;"> <b><a href="mailto:info@aeng.com?subject=Signal Integrity Analysis Quote">Getting a Quotation</a></b> </p> <p style="text-align: left; width: 375px; left: 10px; top: 40px; position: absolute;"> In order to provide a firm fixed quotation for any of the Board level analyses, we will need to see a schematic of the design, a parts list (BOM), and a specification, if one exists. </p> <p style="text-align: left; width: 400px; left: 10px; top: 20px; position: absolute;"> Additionally, for board/SI analysis only: </p> <div style="width: 400px; left: 15px; top: 100px; position: absolute;"> <p style="text-align: left; width: 390px; left: 20px; top: 5px; position: absolute;"> " </p> <p style="text-align: justify; width: 300px; left: 30px; top: 5px; position: absolute;"> Layer stackup information with material types, thicknesses, and manufacturing accuracy. </p> <p style="text-align: left; width: 390px; left: 20px; top: 35px; position: absolute;"> " </p> <p style="text-align: justify; width: 300px; left: 30px; top: 35px; position: absolute;"> I/O assignment for all ASICs and FPGAs including all programmable settings (drive strength, pull-ups, clamps, etc.) </p> <p style="text-align: left; width: 390px; left: 20px; top: 75px; position: absolute;"> " </p> <p style="text-align: justify; width: 300px; left: 30px; top: 75px; position: absolute;"> Some general information about how the board works including output toggling rates </p> <p style="text-align: left; width: 390px; left: 20px; top: 105px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 105px; position: absolute;"> Supply voltage ranges/ripple </p> <p style="text-align: left; width: 390px; left: 20px; top: 125px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 125px; position: absolute;"> If timing analysis is included: </p> <p style="text-align: left; width: 390px; left: 20px; top: 145px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 145px; position: absolute;"> All items listed above </p> <p style="text-align: left; width: 390px; left: 20px; top: 165px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 165px; position: absolute;"> Static timing analysis results for all FPGA/ASICs </p> <p style="text-align: left; width: 390px; left: 20px; top: 185px; position: absolute;"> " </p> <p style="text-align: justify; width: 370px; left: 30px; top: 185px; position: absolute;"> Pin contact inductance </p> <p style="text-align: left; width: 390px; left: 20px; top: 205px; position: absolute;"> " </p> <p style="text-align: justify; width: 300px; left: 30px; top: 205px; position: absolute;"> Timing diagrams for all interfaces (unless available in the datasheets for standard parts) </p> </div> <p style="text-align: justify; width: 375px; left: 10px; top: 360px; position: absolute;"> Please let us know if a Non-Disclosure Agreement (NDA) needs to be put into place. If so, please forward a <b>Mutual NDA Form in MS Word Format to <a href="mailto:Lee@aeng.com">lee@aeng.com</a></b>. AEi Systems can also send its mutual form to you if that is preferred. </p> </div> </div> <div id="secondary_footer_"> <center> <p style="color: Gray;"> <a href="services.htm">Analysis</a> | <a href="spice.htm">SPICE Modeling</a> | <a href="publications.htm">Publications</a><br /> <a href="index.htm">Home</a> | <a href="services.htm">Services</a> | <a href="about.htm"> About Us</a> | <a href="contact.htm">Contact Us</a> | <a href="jobs.htm">Jobs</a><br /> <a href="terms.htm">Terms of Use</a> | <a href="site.htm">Site Map</a><br /> <br /> ©AEi Systems, LLC. All Rights Reserved. </p> </center> </div> </div> </body> </html>